The present invention relates to a master-slave flipflop circuit and a clock control circuit for supplying clock signals to the master-slave flip-flop circuit.
A flip-flop circuit is a type of data storage element and stores data input in synchronism with a clock signal supplied from a clock control circuit. This type of circuit is often used in a register or counter in a microprocessor and the like.
Master-slave flip-flop circuits, which are one type of flipflop circuit, comprise a master circuit and a slave circuit and are controlled by a clock signal whose one cycle comprises data transfer from an input terminal to a data holding element of the master circuit, data holding by a data holding element of the master circuit and data transfer from the data holding element of the master circuit to the data holding element of the slave circuit, and data holding by the data holding element of the slave circuit. The output state is changed at input of an edge of a signal at which data holding in the master circuit is initiated.
Examples of such master-slave flip-flop circuits are shown in (a) "Fundamentals of Semiconductor Integrated Circuits" First Edition, published by Baifukan, Japan (Feb. 20, 1986), page 267 and (b) "Principals of CMOS VLSI Design" - Addison - Wesley Publishing Company, U.S.A. (1985), page 213.
The example of the prior art master-slave flip-flop circuit which is shown in the aforementioned article (a) has a problem in that it may function erroneously due to skew in the clock signals. The skew in the clock signals is a time lag between a clock signal and an inverted clock signal that is introduced by an inverter through which a clock signal (or an inverted clock signal) is passed to produce an inverted clock signal (or an uninverted clock signal).
An example of the prior art master-slave flip-flop circuit which is shown in the aforementioned article (b) attempts to solve the aforementioned problem by using a transfer gate having the same delay time as an inverted and providing inverted and uninverted clock signals at the outputs of the inverter and the transfer gate. But it is difficult to maintain the delay time of the transfer gate exactly equal to the delay time of the inverter irrespective of varying environmental conditions, such as temperature. This means the operation margin is limited. Moreover, a transfer gate does not have driving power. Restriction on the fan-out is therefore severe. This means the amount of hardware, particularly the clock control circuitry per flip-flop circuit, is increased.